technical data 19 dual jk flip-flop high-voltage silicon-gate cmos the iw4027b is a dual jk flip-flop which is edge-triggered and features independent set, reset, and clock inputs. data is accepted when the clock is low and transferred to the output on the positive- going edge of the clock. the active high asynchronous reset and set are independent and override the j, k, or clock inputs. the outputs are buffered for best system performance. ? operating voltage range: 3.0 to 18 v ? maximum input current of 1 a at 18 v over full package- temperature range; 100 na at 18 v and 25 c ? noise margin (over full package temperature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply iw4027b ordering information iw4027bn plastic IW4027BD soic t a = -55 to 125 c for all packages logic diagram pin 16 =v cc pin 8 = gnd pin assignment function table inputs outputs set reset clock j k q n+1 q n+1 lhxxxl h hl xxxh l hh xxxh h l l l l no change ll hlhl ll lhlh l l h h qn qn x = don?t care qn+1 = state after clock positive transition
iw4027b 20 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +20 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
iw4027b 21 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v -55 c25 c 125 c unit v ih minimum high-level input voltage v out =0.5 v or v cc - 0.5 v v out =1.0 v or v cc - 1.0 v v out =1.5 v or v cc - 1.5 v 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low -level input voltage v out =0.5 v or v cc - 0.5 v v out =1.0 v or v cc - 1.0 v v out =1.5 v or v cc - 1.5 v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high-level output voltage v in =gnd or v cc 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low-level output voltage v in =gnd or v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 a i cc maximum quiescent supply current (per package) v in = gnd or v cc 5.0 10 15 20 1.0 2.0 4.0 20 1.0 2.0 4.0 20 30 60 120 600 a i ol minimum output low (sink) current v in = gnd or v cc v ol =0.4 v v ol =0.5 v v ol =1.5 v 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 ma i oh minimum output high (source) current v in = gnd or v cc v oh =4.6 v v oh =2.5 v v oh =9.5 v v oh =13.5 v 5.0 5.0 10 15 -0.64 ?2.0 ?1.8 ?4.2 -0.51 ?1.6 ?1.3 ?3.4 -0.36 ?1.15 ?0.9 ?2.4 ma
iw4027b 22 ac electrical characteristics (c l =50pf, r l =200 k ? , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c25 c 125 c unit f max maximum clock frequency 5.0 10 15 3.5 8 12 3.5 8 12 1.75 4 6 mhz t plh , t phl maximum propagation delay, clock to q or q 5.0 10 15 300 130 90 300 130 90 600 260 180 ns t plh maximum propagation delay, set to q or reset to q 5.0 10 15 300 130 90 300 130 90 600 260 180 ns t phl maximum propagation delay, set to q or reset to q 5.0 10 15 400 170 120 400 170 120 800 340 240 ns t tlh , t thl maximum output transition time, any output 5.0 10 15 200 100 80 200 100 80 400 200 160 ns c in maximum input capacitance - 7.5 pf timing requirements (c l =50pf, r l =200 k ? , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c25 c 125 c unit t w minimum pulse width, clock 5.0 10 15 140 60 40 140 60 40 280 120 80 ns t w minimum pulse width, set or reset 5.0 10 15 180 80 50 180 80 50 360 160 100 ns t su minimum setup time 5.0 10 15 200 75 50 200 75 50 400 150 100 ns t r , t f maximum input rise or fall time, clock 5.0 10 15 45 5 2 45 5 2 90 10 4 s
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